Conventional disk drives have employed peak detection techniques in order to recover digital data written as saturation recording onto a magnetizable surface media of a rotating disk. With peak detection techniques, it is necessary to space flux transitions sufficiently apart so that analog peaks in the recovered data stream may be identified and the corresponding data recovered. In order to achieve reasonable bandwidths in data channels, it has been customary to employ data coding techniques. One such technique has been to use a (1,7) RLL code. in this code, flux transitions can be no closer together than every other clock bit time period ("bit cell") nor farther apart than eight clock bit cells. (1,7) RLL codes are known as "rate two-thirds" codes, in the sense that two data bits are coded into three code bits. Thus, with a rate two-thirds code, one third of the user storage area of the storage disk is required for code overhead.
One way to decrease the code overhead is to employ a code in which flux transitions are permitted in adjacent bit cells. One such code is a (0,4,4) code. The (0,4,4) code is generally thought of as a rate eight-ninths code, meaning that nine code bits are required for eight incoming data bits. (Theoretically, the (0,4,4) code ratio is somewhat higher, approaching 0.961) Thus, this code is significantly more efficient than a rate two-thirds code, such as (1,7) RLL. Use of a (0,4,4) code results in a significantly greater net user data storage capacity on the disk surface, given a constant bit cell rate. However, when flux transitions occur in adjacent bit cells, as is the case with a (0,4,4) code, intersymbol interference ("ISI") results. Conventional peak detection techniques are not effective or reliable in recovering data coded in an eight-ninths code format, such as (0,4,4).
The zero in the (0,4,4) code denotes that flux transitions may occur in directly adjacent bit cells of the coded serial data stream. The first "4" denotes that a span of no more than four zeros occurs between ones in the encoder output. The second "4" signifies that the bit cell stream has been divided into two interleaves: an even interleave, and an odd interleave; and, it denotes that there can be a span of no more than four zeros between ones in the encoder output of either the odd interleave or the even interleave.
It is known that partial response signalling enables improved handling of ISI and allows more efficient use of the bandwidth of a given channel. Since the nature of ISI is known in these systems, it may be taken into account in the decoding/detection process. Partial response transmission of data lends itself to synchronous sampling and provides an elegant compromise between error probability and the available spectrum. The partial response systems described by the polynomials 1+D, 1-D, and 1-D.sup.2 are known as duobinary, dicode and class IV (or "PR4"), respectively, where D represents one bit cell delay and D.sup.2 represents 2 bit cell delays (and further where D=e.sup.-j.omega.T, where .omega. is a frequency variable in radians per second and T is the sampling time interval in seconds). The PR4 magnitude response plotted in FIG. 1 hereof and given the notation .vertline.1-D.sup.2 .vertline. emphasizes midband frequencies and results in a read channel with increased immunity to noise and distortion at both low and high frequencies. In magnetic recording PR4 is a presently preferred partial response system, since there is a close correlation between the idealized PR4 spectrum as graphed in FIG. 1, and the natural characteristics of a magnetic data write/read channel.
In order to detect user data from a stream of coded data, not only must the channel be shaped to a desired partial response characteristic, such as the PR4 characteristic, but also a maximum likelihood ("ML") sequence estimation technique is needed. The maximum likelihood sequence estimation technique determines the data based upon an analysis of a number of consecutive data samples taken from the coded serial data stream, and not just one peak point as was the case with the prior peak detection methods.
One maximum likelihood sequence estimation algorithm is known as the Viterbi detection algorithm, and it is well described in the technical literature. Application of the Viterbi algorithm to PR4 data streams within a magnetic recording channel is known to improve detection of original symbol sequences in the presence of ISI and also to improve signal to noise ratio over comparable peak detection techniques.
In an article entitled "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel" appearing in IEEE Trans. on Communications, vol. Com-34, No. 5, May 1986, pp. 434-461, authors Wood and Peterson explain the derivation of PR4 as being formed by subtracting waveforms two bit intervals apart, thereby forming an analog domain ternary "eye" pattern graphed herein in FIG. 2.
The Viterbi algorithm provides an iterative method of determing the "best" route along the branches of a trellis diagram, such as the one shown in FIG. 3 hereof, for example. If, for each trellis branch, a metric is calculated which corresponds to the logarithm of the probability for that branch, then the Viterbi algorithm may be employed to determine the path along the trellis which accumulates the highest log probability, i.e., the "maximum likelihood" sequence. Since the Viterbi algorithm operates upon a sequence of discrete samples {Yk}, the read signal is necessarily filtered, sampled, and equalized.
While PRML has been employed in communications signalling for many years, it has only recently been applied commercially within magnetic hard disk drives. One recent application is described in a paper by Schmerbeck, Richetta, and Smith, entitled "A 27 MHz Mixed Analog/Digital Magnetic Recording Channel DSP Using Partial Response Signalling with Maximum Likelihood Detection", Proc. 1991 IEEE International Solid State Circuits Conference, pp. 136-137, 304, and pp. 96, 97 and 265 Slide Supplement. While the design reported by Schmerbeck et al. appears to have worked satisfactorily, it has drawbacks and limitations which are overcome by the present invention. One drawback of the reported approach was its design for transducers of the ferrite MiG type or of the magnetoresistive type which simplified channel equalization requirements. Another drawback was the use of a single data transfer rate which significantly simplified channel architecture. A further drawback was the use of a dedicated servo surface for head positioning within the disk drive, thereby freeing the PR4; ML data channel from any need for handling of embedded servo information or for rapid resynchronization to the coded data stream following each embedded servo sector.
Prior Viterbi detector architectures and approaches applicable to processing of data sample sequences taken from a communications channel or from a recording device are also described in the Dolivo et al. U.S. Pat. No. 4,644,564. U.S. Pat. No. 4,504,872 to Peterson describes a digital maximum likelihood detector for class IV partial response signalling. An article by Roger W. Wood and David A. Peterson, entitled: "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel" IEEE Trans. on Comm. Vol. Com-34, No. 5, May 1986, pp. 454-466 describes application of Viterbi detection techniques to a class IV partial response in a magnetic recording channel. An article by Roger Wood, Steve Ahigrim, Kurt Hallarnasek and Roger Stenerson entitled: "An Experimental Eight-Inch Disc Drive with One-Hundred Megabytes per Surface", IEEE Trans. on Magnetics, Vol. Mag-20, No. 5, September 1984, pp 698-702 describes application of class IV partial response encoding and Viterbi detection techniques as applied within an experimental disk drive. A digital Viterbi detector capable of withstanding lower signal to noise ratios, is described in Matsushita et al. U.S. Pat. No. 4,847,871. These documents are representative examples of the known state of the prior art.
When zoned data recording techniques, embedded servo sectors, and e.g. thin-film heads are employed in a high performance, very high capacity, low servo overhead disk drive, the prior approaches are not adequate, and a hitherto unsolved need has arisen for an approach incorporating PR4, ML techniques into a high capacity, high performance, low cost disk drive architecture including architectural features such as e.g. thin-film heads, embedded sector servo based head positioning, and zone-data-recording techniques.
In particular, the prior art has not adequately addressed the stringent timing control requirements needed within such an architecture. In prior art approaches, phase locked loops have been employed to provide for timing control for proper sampling of analog data. In such prior art circuits, a loop filter within the PLL has provided operating point memory and has established the dynamics of the PLL. In the prior systems, there were two basic timing control modes of operation: READ and NON-READ. Locking the clock recovery PLL to a frequency reference during non-read initialized the operating point and continuously refreshed the operating point memory. Usually, the memory had been implemented as a charge-holding capacitor which, except for the fact of periodic updating, would otherwise lose its charge over time due to leakage, parasitic currents, etc.
The timing loop dynamics are important in a sampled data recovery system. Performance determines both the time required to recover from transient conditions as well as the quality of the recovered clock. The PLL must quickly acquire the data clock frequency and phase when beginning to read data, so that the amount e.g. of disk area that must be assigned for this acquisition time is minimized. Transient conditions occur when initializing a READ operation due to the phase and frequency of the data differing from the phase and frequency of the clock recovery circuit at the switchover from NON-READ to READ mode. While the operating point memory reduces the size of the frequency and phase step between NON-READ and READ modes, the memory does not eliminate such step size, because of e.g. drifts in disk rotational speed and reference frequency. Often the loop filter has been a compromise between good transient response and good recovered clock quality. For good clock quality, the loop bandwidth should be narrow so that phase noise in the data is attenuated in the recovered clock control signal. For fastest transient response, the timing loop bandwidth should be made as wide as possible.
One prior approach for timing control has been employed in conventional peak detection of data, as noted above. In peak detection the peaks of the readback signal represent the encoded data "ones". The "zeros" are represented by a lack of a signal peak. Phase locked loop techniques have been used to lock onto the peaks of the readback signal and generate a data clock that is then used to synchronize the detected data peaks ("raw data") into fixed clock time intervals. This framing of the raw data is needed to eliminate e.g. spindle jitter and noise otherwise associated with disk drive magnetics, electronics, and mechanics.
In conventional disk drives employing peak detection techniques, during NON-READ mode, the timing PLL has been locked to a frequency reference that is very near the data clock frequency, so that upon transition to READ mode, the PLL takes less time to lock to the data because it is already close in frequency. A typical peak detection channel timing PLL has included a phase/frequency detector, a charge pump, and a voltage controlled oscillator (VCO). Logic gating at the input of the phase/frequency detector has been employed to lock to a frequency reference during NON-READ and then to lock to the read signal during READ. This simple switching approach has been possible because the reference clock signal and the raw data were both logic waveforms where the frequency and phase information are contained in the logic transition edges. The PLL operating frequency that is acquired from the frequency reference is "remembered" when switching to READ mode e.g. by storage across a capacitor at the output of the charge pump. The capacitor holds the charge associated with a given frequency. This approach, while working satisfactorily within peak detection data recovery channels, has not been compatible with timing recovery and control for sampled data systems, such as PR4,ML.
In a PR4,ML system, a PLL has been needed to generate a coherent clock, since the data samples must be taken at particular places on the readback waveform. Phase and frequency of the data is detected by digitally processing the data samples rather than by comparing signal transition edges as in peak detection techniques. The digital circuitry processes the data samples to make phase/frequency error estimates and then sends these digital estimates to a timing control DAC. For the same reasons as discussed above in connection with peak detection, locking to a reference frequency during NON-READ mode is desirable. Separate phase/frequency detector circuits must be used for the data samples and the reference clock, since these signals are different in nature. During NON-READ mode the circuitry for sensing the reference clock is selected to control the PLL oscillator frequency, and during READ mode, the data sample sensing circuitry has to be used.
A prior approach followed by IBM has been described in several articles including Coker et al., "Implementation of PRML in a Rigid Disk Drive", IEEE Trans, on Magnetics, Vol. 27, No. 6, November 1991, pp 4538-4543; and, Cideciyan et al, "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communications, Vol. 10, No. 1, January 1992, pp 38-56. In the described approach, a common analog loop compensation filter was used during both READ mode and NON-READ mode. While that approach had the advantage of automatically remembering the PLL operating point as had been the case with prior peak detection data channels, it did not enable separate loop compensation during the two different modes and did not facilitate the use of a digital loop filter during READ mode sample times.
Another technique known to the prior art in conjunction with peak detection techniques is generally referred to as "zero phase start". This technique enables a phase pause of controllable duration to be applied within a timing control loop. In the prior art peak detection timing loop described above, the VCO has had an ENABLE input that allows for controlled starting and stopping of the oscillator. Thus, when an ENABLE control is asserted, the oscillator will begin oscillating in a known state. Thus, the clock transition rising edges, which contain the important timing aspect of the resultant clock signal, occur at a fixed delay interval after assertion of the ENABLE control signal. The prior zero phase start logic sensed a transition of a read gate control signal RDGATE from inactive to active (indicating initiation of READ mode) and deasserted ENABLE, stopping the VCO. Upon arrival of a subsequent raw data transition edge in the analog data stream at the zero phase logic, the ENABLE control signal is reasserted and the timing loop VCO was restarted. A timing delay block matched the delays associated with detecting the raw data edge and restart of the VCO, so that the raw data edge and the first clock edge put out by the timing loop VCO coincided at the input to the phase/frequency detector simultaneously, or nearly simultaneously. Thus, the starting phase error was near zero, and PLL acquisition time was reduced.
A representative state of the prior art is found in an article by Dolivo et al, entitled "Fast Timing Recovery for Partial-Response Signalling Systems", Proc. of ICC '89 (IEEE), Boston, Mass., Jun. 11-14, 1989, (five page paper); U.S. Pat. No. 4,122,501 to Sordello et al. and entitled "System for Recording and Reading Back Data on a Recording Media"; and, U.S. Pat. No. 5,065,116 to Ueda et al., and entitled "Zero Phase Start Compensation for VCO". These prior approaches have not fully satisfied the requirements for a high performance, multi-mode timing loop for synchronizing data recovery in a sampled data system.